Implementing a RISC-V Pipeline CPU on a Kintex 7 Series FPGA Board

2023-04-2

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project lapse time: 2022-06-4 - 2022-07-15

Introduction

For my computer organization and design course's final project, I decided to implement a RISC-V pipeline CPU on a Kintex 7 series FPGA board. I also created a classic minesweeper game that could run on the CPU and used VGA to display graphics.

RISC-V Pipeline CPU Implementation

The RISC-V pipeline CPU was implemented in Verilog HDL. The pipeline design was a classic 5-stage RISC-V pipeline, which consisted of the following stages:

  1. Instruction Fetch (IF)
  2. Instruction Decode (ID)
  3. Execution (EX)
  4. Memory Access (MEM)
  5. Write Back (WB)
RISC-V Pipeline

The CPU was designed to support a subset of the RV32I instruction set, which is the base integer instruction set of RISC-V. the CPU also included support for branching and jumping instructions.

I also used the ModelSim simulator to simulate the CPU for debugging purposes,

ModelSim Simulator

After the design was completed, I used Xilinx ISE to synthesize the design and generate the bitstream for the FPGA board. I then programmed the FPGA board and verified that the CPU was functioning correctly by running a series of test programs.

FPGA Board

Minesweeper Game Implementation

The minesweeper game was written in C and compiled using the RISC-V GCC compiler. The game used VGA to display graphics on a monitor connected to the FPGA board.

The game logic was implemented using a simple algorithm that randomly placed mines on the game board and calculated the number of mines adjacent to each cell. The game also included a timer to track the player's score.

To display the game board, I used the VGA interface on the FPGA board to output the game graphics to the monitor. The VGA interface was implemented using Verilog HDL and generated the necessary signals to drive the monitor.

Minesweeper Game

Conclusion

Overall, this project was a great learning experience for me. It gave me the opportunity to work with both hardware and software and integrate them into a complete system. I was able to gain experience in Verilog HDL, FPGA programming, and RISC-V CPU design. The project also allowed me to explore the use of VGA to display graphics, which was a valuable experience.

I believe that the skill set I gained from this project will be very useful in my future career.